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| features ? pfc with ir proprietary ?one cycle control? ? continuous conduction mode (ccm) boost type pfc ? no line voltage sense required ? programmable switching frequency (50khz-200khz) ? programmable output overvoltage protection ? brownout and output undervoltage protection ? cycle-by-cycle peak current limit ? soft start ? user initiated micropower ?sleep mode? pfc one cycle control pfc ic ir1150s (pbf) ir1150is (pbf) www.irf.com 1 ir1150 application diagram data sheet no. pd60230 revaa description the pfc ir1150 is a power factor correction (pfc) control ic designed to operate in continuous conduction mode (ccm) over a wide range input line voltages. the ir1150 is based on ir's proprietary "one cycle control" (occ) technique providing a cost effective solution for pfc. the proprietary control method allows major reductions in component count, pcb area and design time while delivering the same high system performance as traditional solutions. the ic is fully protected and eliminates the often noise sensitive line voltage sensing requirements of existing solutions. the ir1150 features include programmable switching frequency, programmable dedicated over voltage protection, soft start, cycle-by-cycle peak current limit, brownout, open loop, uvlo and micropower startup current. in addition, for low standby power requirements (energy star, 1w standby, blue angel, etc.), the ic can be driven into sleep mode with total current consumption below 200a, by pulling the ovp pin below 0.62v. package 8-lead soic ? open loop protection ? maximum duty cycle limit of 98% ? user programmable fixed frequency operation ? min. off time of 150-350ns over freq range ? v cc under voltage lockout ? internally clamped 13v gate drive ? fast 1.5a peak gate drive ? micropower startup (<200 a) ? latch immunity and esd protection ? parts also available lead-free isns 3 comp 5 vfb 6 ovp 4 freq 2 vcc 7 gate 8 com 1 ir1150 -+ bridge v out rtn + ac neutral ac line vcc + http:///
ir1150s/ir1150is (pbf) www.irf.com 2 parameters symbols min. typ. max. units remarks supply voltage v cc 15 18 20 v junction temperature t j -25 ? 125 c ambient temperature t a 0 ? 70 c ir1150s ambient temperature t a -25 ? 85 c ir1150is switching frequency f sw 50 ? 200 khz absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltages are absolute voltages referenced to com. thermal resistance and power dissipation are measured under board mounted and still air conditions. parameters symbols min. max. units remarks v cc voltage v cc -0.3 22 v not internally clamped freq. voltage v freq. -0.3 10.5 v i sns voltage v isns -10 3 v v fb voltage v fb -0.3 10.5 v comp voltage v comp -0.3 10 v gate voltage v gate -0.3 18 v continuous gate current i gate -5 5 ma max peak gate current i gatepk -1.5 1.5 a junction temperature t j -40 150 o c storage temperature t s -55 150 o c thermal resistance r ja ? 128 c/w soic-8 package power dissipation p d ? 675 mw soic-8 t amb = 25 o c esd protection v esd ? 2 kv human body model* recommended operating conditions recommended operating conditions for reliable operation with margin electrical characteristics the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range t j from ? 25 c to 125c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc =15v is assumed for test condition parameters symbols min. typ. max. units remarks v cc turn-on threshold v cc on 12.2 12.7 13.2 v v cc turn-off threshold v cc uvlo 10.2 10.7 11.2 v (under voltage lock out) v cc turn-off hysteresis v cc hyst 1.8 ? 2.2 v supply section *per eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k ? series resistor) http:/// www.irf.com 3 ir1150s/ir1150is (pbf) electrical characteristics cont. the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range t j from ? 25 c to 125c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc =15v is assumed for test condition. oscillator section parameters symbols min. typ. max. units remarks switching frequency f sw 50 ? 200 khz r set = 165k ? -37k ? approx. initial accuracy f sw acc ?? 5 %t a = 25 o c voltage stability v stab ? 0.2 3 % 13v ir1150s/ir1150is (pbf) www.irf.com 6 lead assignments & definitions block diagram 8 7 6 5 4 3 2 1 lead assignment pin# symbol description 1 2 3 4 5 6 7 8 com freq i ovp/en comp v v gate ground frequency set current sense overvoltage fault detect / enable voltage loop compensation output voltage sense ic supply voltage gate drive output com freq i ovp/en comp gate 8 lead soic ir1150s sns v cc v fb sns fb cc v ref fault q s rq 1.0v + v m clock reset max duty cycle li mit - fault uvlo bias & references 1.055v ref sleep 0. 5v fault fault protection output under voltage open loop protecti on 8 2 1 7 4 6 5 3 ovp/en comp v i v freq gate com cc sns fb http:/// www.irf.com 7 ir1150s/ir1150is (pbf) the pfc ir1150 is intended for boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. the ic operates with two loops; an inner current loop and an outer voltage loop. the inner current loop is fast, reliable and does not require sensing of the input voltage in order to create a current reference. this inner current loop sustains the sinusoidal profile of the average input current based on the dependency of the pulse width modulator duty cycle on the input line voltage in order to determine the analogous input line current. thus, the current loop uses the embedded input voltage signal to control the average input current to follow the input voltage. the ir1150 enables excellent thd performance. in light load conditions, a small distortion occurs at zero- crossing due to the finite boost inductance but this is negligible and well within en61000-3-2 class d specifications. the outer voltage loop controls the dc bus voltage. this voltage is fed into the voltage error amplifier to control the slope of the integrator ramp and sets the amplitude of the average input current. the two loops combine to control the amplitude, phase and shape of the input current, with respect to the input voltage, giving near-unity power factor. the ic is designed for robust operation and pro- vides protection from system level over current, over voltage, under voltage, and brownout conditions. ic supply the uvlo circuit monitors the v cc pin and maintains the gate drive signal inactive until the v cc pin voltage reaches the uvlo turn on threshold, (v cc on ). as soon as the v cc voltage exceeds this threshold, provided that the v fb pin voltage is greater than 20%v ref , the gate drive will begin switching (under soft start) and increase the pulse width to its maximum value as demanded by the output voltage error amplifier. if the voltage on the v cc pin falls below the uvlo turn off threshold, (v cc uvlo ), the ic turns off, gate drive is terminated, and the turn on threshold must again be exceeded in order to re-start the process and move into soft start mode. soft start soft start controls the rate of rise of the output voltage error amplifier in order to obtain a linear control of the increasing duty cycle as a function of time. the soft start time is controlled by voltage error amplifier compensation components selected, and is user programmable based on desired loop crossover frequency. frequency select the switching frequency of the ic is programmable by an external resistor at the freq pin. the design incorporates min/max restrictions such that the minimum and maximum operating frequency fall within the range of 50-200khz. gate drive the gate drive is a totem pole driver with 1.5a capa bility. if higher currents are required, additional external drivers can be used. general description http:/// ir1150s/ir1150is (pbf) www.irf.com 8 com: ground this is the ground potential pin of the integrated con- trol circuit. all internal devices are referenced to this point. v fb : output voltage feedback the output voltage of the boost converter is sensed via a resistive divider and fed into this pin, which is the inverting input of the output voltage error amplifier. the impedance of the divider string must be low enough so as to not introduce substantial error due to the input bias currents of the amplifier, yet high enough so as to minimize power dissipation. a typical value of external divider impedance is 1m ? . the error amplifier is a transconductance type which yields high output impedance, thus increasing the noise immunity of the error amplifier output. this also eliminates input divider string interaction with compensation feedback capacitors and reducing the loading of divider string due to a low impedance output of the amplifier. comp: voltage loop compensation external circuitry from this pin to ground compensates the system voltage loop and soft start time. this is the output of the voltage error amplifier. this pin will be discharged via internal resistance when a fault mode occurs. gate: gate drive output this is the gate drive output of the ic. drive voltage is internally limited and provides 1.5a peak with matched rise and fall times. freq: frequency set this is the user programmable frequency pin. an external resistor from this pin to the com pin pro- grams the frequency. the operational switching fre- quency range for the device is 50khz ? 200khz. i sns : current sense input this pin is the inverting current sense input & peak current limit. the voltage at this pin is the negative voltage drop, sensed across the system current sense resistor, representing the inductor current. this voltage is fed into the peak current limit pro- tection comparator with threshold arond -1v. this pro- tection circuit incorporates a leading edge blanking circuit following the comparator to improve noise immu nity of the protection process. the current sense signal is also fed into the current sense amplifier. the signal is amplified, filtered of high frequency noise and then injected into a sum- ming node where it is subtracted from the compen- sation voltage v comp . the signal on this pin must be previously filtered with an rc cell to provide additional noise immunity. the input impedance of this pin is 5k ? . v cc : supply voltage this is the supply voltage pin of the ic and it is monitored by the under voltage lockout circuit. it is possible to turn off the ic by pulling this pin below the minimum turn off threshold voltage, without damage to the ic. to prevent noise problems, a bypass ceramic capacitor connected to v cc and com should be placed as close as possible to the ir1150s. this pin is not internally clamped, therefore damage will occur if the maximum voltage is exceeded. ovp/en: over voltage protection / enable this pin is the input to the over voltage protection comparator the threshold of which is internally pro- grammed to 105.5% of v ref . a resistive divider feeds this pin from the output volt- age to com and inhibits the gate drive whenever the threshold is exceeded. normal operation resumes when the voltage level on this pin decreases to be- low the pin threshold. this pin is also used to activate ?sleep? mode by pulling the voltage level below 0.62v (typ). detailed pin description http:/// www.irf.com 9 ir1150s/ir1150is (pbf) uvlo mode the ic remains in the uvlo condition until the voltage on the v cc pin exceeds the v cc turn on threshold voltage, v cc on. during the time the ic remains in the uvlo state, the gate drive circuit is i nactive and the ic draws a quiescent current of i cc start. the uvlo mode is accessible from any other state of operation whenever the ic supply voltage condition of v cc < v cc uvlo occurs. standby mode the ic is in this state if the supply voltage has exceeded v cc on and the v fb pin voltage is less than 20% of v ref . the oscillator is running and all internal circuitry is biased in this state but the gate is inactive. this state is accessible from any other state of operation except ovp. the ic enters this state whenever the v fb pin voltage has decreased to 50% of v ref when operating in normal mode or during a peak current limit fault condition, or 20% v ref when operating in soft start mode. soft start mode this state is activated once the v cc voltage has exceeded v ccon and the v fb pin voltage has exceeded 20% of v ref . the soft start time, which is defined as the time required for the duty cycle to linearly increase from zero to maximum, is dependent upon the values selected for compensation of the voltage loop pin comp to pin com. throughout the soft start cycle, the output of the voltage error amplifier (pin comp) charges through the compensation network. this forces a linear rise of the voltage at this node which in turn forces a linear increase in the gate drive duty cycle from 0. this controlled duty cycle reduces system component stress during start up conditions as the input current amplitude is increasing linearly. normal mode the ic enters normal operating mode once the soft start transition has been completed. at this point the gate drive is switching and the ic draws a maximum of i cc from the supply voltage source. the device will initiate another soft start sequence in the event of a shutdown due to a fault, which activates the protection circuitry, or if the supply voltage drops below the uvlo turn off threshold of v cc uvlo. fault protection mode the fault mode will be activated when any of the protection circuits are activated. the ic protection circuits include supply voltage under voltage lockout (uvlo), output over voltage protection (ovp), open loop protection (olp), output undervoltage protection (ouv), and peak current limit protection (i pk limit ). sleep mode the sleep mode is initiated by pulling the ovp pin below 0.62v (typ). in this mode the ic draws a very low quiescent supply current. operating states http:/// ir1150s/ir1150is (pbf) www.irf.com 10 ac power on gate inactive oscillator inactive uvlo v < v gate inactive oscillator inactive stand - by v < 20 % v gate inactive oscillator active soft start gate active oscillator active pulse width increasing 0 - 97 % duty cycle normal gate active oscillator active ovp fault gate inactive oscillator active fault present pulseterminated oscillator active sleep v < 0.7v gate inactive oscillator inactive i = 200ua v > v i = 200ua cc ccon cc ccon cc max cc max ovp fb ref v > 20%v fb ref v < 50%v fb ref v < v cc cc uvlo v < v cc cc uvlo v < v cc cc uvlo v < v cc cc uvlo v < v cc cc uvlo v < 20% v fb ref v > 80%v fb ref v < 80% v fb ref v < 50%v fb ref v > 0.7v ovp v < 0.7v ovp v < 0.7v ovp v < 0.7v ovp v < 0.7v ovp v < ovp 101% v ref v > ovp 105% v ref v > ovp 105% v ref v < 0.7v ovp i= 4ma cc max i= 28 ma cc max i pk limit v >-1.0v isns v < -1 .0v isns v < -1 .0v isns v >-1.0v isns v <-1 .0v isns state & transitions diagram http:/// www.irf.com 11 ir1150s/ir1150is (pbf) 9 v 10 v 11 v 12 v 13 v -50 c 0 c 50 c 100 c 150 c temperature vcc uvlo thresholds vcc on vcc uvlo 0 khz 50 khz 100 khz 150 khz 200 khz 250 khz 300 khz 0 k 50 k 100 k 150 k 200 k programming resistor switching frequenc y 0.01 0.1 1 10 100 5 v 10 v 15 v 20 v 25 v supply voltage i supply fig.1 - supply current fig. 2 - under voltage lockout vs. temperature fig. 4 - oscillator frequency vs. temperature fig. 3 - oscillator frequency vs. programming resistor v cc uvlo thresholds v cc uvlo v cc on 0 khz 50 khz 100 khz 150 khz 200 khz 250 khz -50 c 0 c 50 c 100 c 150 c temperature switching frequency (typ.) - f sw rf=37k rf=78k rf=165k r f r f r f http:/// ir1150s/ir1150is (pbf) www.irf.com 12 30 us 35 us 40 us 45 us 50 us -50 c 0 c 50 c 100 c 150 c temperature ea transconductance (typ.) - g m 10 ua 20 ua 30 ua 40 ua 50 ua 60 ua -50 c 0 c 50 c 100 c 150 c temperature error amplifier current source/sin k io (source) io (sink) 2.30 2.40 2.50 2.60 2.70 -50 c 0 c 50 c 100 c 150 c temperature current sense dc gai n 6.85 v 6.90 v 6.95 v 7.00 v 7.05 v 7.10 v -50 c 0 c 50 c 100 c 150 c temperature reference voltage (typ.) - v ref fig. 5 - reference voltage fig. 6 - voltage error amplifier transconductance fig.7 - voltage error amplifier source/sink current fig. 8 - current sense amplifier dc gain http:/// www.irf.com 13 ir1150s/ir1150is (pbf) t vcc 13.0v (typ) 11.0v (typ) uvlo normal uvlo v cc under voltage lockout output protection ir1150 timing diagrams t 106% v 51% v olp ovp olp 19% v soft start ouv 100% v normal 82% v ref ref ref ref ref feedback voltage (v fb ) ic supply voltage (v cc ) http:/// ir1150s/ir1150is (pbf) www.irf.com 14 case outline 01-6027 01-0021 11 (ms-012aa) 8-lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & tolerancing per asme y14.5m-1994. 2 . c o n t r o l l in g d im e n s io n : m il l im e t e r 3. dimensions are shown in millimeters [inc hes]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exceed 0.25 [.010]. 7 d im e n s io n is t h e l e n g th o f l e a d f o r s o l d e r in g to a subs trate. mold protrusions not to exceed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 b asic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 b asic 0.635 b asic http:/// www.irf.com 15 ir1150s/ir1150is (pbf) tape & reel information dimensions are shown in millimeters (inches) 330.00 (12.992) max. 14.40 ( .566 ) 12.40 ( .488 ) notes : 1. controlling dimension : millimeter. 2. outline conforms to eia-481 & eia-541. feed direction terminal number 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) notes: 1. outline conforms to eia-481 & eia-541. 2. controlling dimension : millimeter. http:/// ir1150s/ir1150is (pbf) www.irf.com 16 world headquarters: 233 kansas street, el segundo, california 90245 tel: (310) 252-7105 http://www.irf.com/ data and specifications subject to change without notice. 6/13/2005 the ir1150s(pbf) has been designed and qualified for the consumer market the ir1150is(pbf) has been designed and qualified for the industrial market qualification standards can be found on ir?s web site. part marking information lot code ? lead free released non-lead free released p ? marking code ( ) basic part 8-lead soic ir1150str order ir1150str 8-lead soic ir1150istr order ir1150istr lead-free part 8-lead soic ir1150s order ir1150strpbf 8-lead soic ir1150istr order ir1150istrpbf order information http:/// |
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